Cambridge A Level Computer Science 9608 — 2015 May/June Paper 1 · Variant 3

This document consists of 16 printed pages. DC (AC/SG) 101101/3 © UCLES 2015 [Turn over Cambridge International Examinations Cambridge International Advanced Subsidiary and Advanced Level * 1 4 2 4 6 5 1 9 2 4 * COMPUTER SCIENCE 9608/13 Paper 1 Theory Fundamentals May/June 2015 1 hour 30 minutes Candidates answer on the Question Paper. No Additional Materials are required. No calculators allowed. READ THESE INSTRUCTIONS FIRST Write your Centre number, candidate number and name on all the work you hand in. Write in dark blue or black pen. You may use an HB pencil for any diagrams, graphs or rough working. Do not use staples, paper clips, glue or correction fluid. DO NOT WRITE IN ANY BARCODES. Answer all questions. No marks will be awarded for using brand names of software packages or hardware. At the end of the examination, fasten all your work securely together. The number of marks is given in brackets [ ] at the end of each question or part question. The maximum number of marks is 75.

2 9608/13/M/J/15 © UCLES 2015 1 (a) (i) Using two’s complement, show how the following denary numbers could be stored in an 8-bit register: 124 –77 [2] (ii) Convert the two numbers in part (a) (i) into hexadecimal. 124 … –77 … [2] (b) Binary Coded Decimal (BCD) is another way of representing numbers. (i) Write the number 359 in BCD form. … [1] (ii) Describe a use of BCD number representation. … … [2]

3 9608/13/M/J/15 © UCLES 2015 [Turn over 2 Assemblers translate from assembly language to machine code. Some assemblers scan the assembly language program twice; these are referred to as two-pass assemblers. The following table shows five activities performed by two-pass assemblers. Write 1 or 2 to indicate whether the activity is carried out during the first pass or during the second pass. Activity First pass or second pass any symbolic address is replaced by an absolute address any directives are acted upon any symbolic address is added to the symbolic address table data items are converted into their binary equivalent forward references are resolved [5]

4 9608/13/M/J/15 © UCLES 2015 3 (a) Give the definition of the terms firewall and authentication. Explain how they can help with the security of data. Firewall … … … … … … Authentication … … … … [3] (b) Describe two differences between data integrity and data security. … … … … … … [2] (c) Data integrity is required at the input stage and also during transfer of the data. (i) State two ways of maintaining data integrity at the input stage. Use examples to help explain your answer. … … … … … … [3]

5 9608/13/M/J/15 © UCLES 2015 [Turn over (ii) State two ways of maintaining data integrity during data transmission. Use examples to help explain your answer. … … … … … … [3]

6 9608/13/M/J/15 © UCLES 2015 4 (a) There are two types of RAM: dynamic RAM (DRAM) and static RAM (SRAM). Five statements about DRAM and SRAM are shown below. Draw a line to link each statement to the appropriate type of RAM. Statement Type of RAM requires data to be refreshed periodically in order to retain the data has more complex circuitry DRAM does not need to be refreshed as the circuit holds the data as long as the power supply is on requires higher power consumption which is significant when used in battery-powered devices SRAM used predominantly in cache memory of processors where speed is important [5]

7 9608/13/M/J/15 © UCLES 2015 [Turn over (b) Describe three differences between RAM and ROM. … … … … … … [3] (c) DVD-RAM and flash memory are two examples of storage devices. Describe two differences in how they operate. … … … … … [2]

8 9608/13/M/J/15 © UCLES 2015 5 (a) Name and describe three buses used in the von Neumann model. Bus 1 … Description … … … Bus 2 … Description … … … Bus 3 … Description … … … [6] (b) The sequence of operations shows, in register transfer notation, the fetch stage of the fetch- execute cycle. 1 MAR ← [PC] 2 PC ← [PC] + 1 3 MDR ← [[MAR]] 4 CIR ← [MDR] • [register] denotes contents of the specified register or memory location • step 1 above is read as “the contents of the Program Counter are copied to the Memory Address Register” (i) Describe what is happening at step 2. … … [1] (ii) Describe what is happening at step 3. … … … [1]

9 9608/13/M/J/15 © UCLES 2015 [Turn over (iii) Describe what is happening at step 4. … … [1] (c) Describe what happens to the registers when the following instruction is executed: LDD 35 … … … … [2] (d) (i) Explain what is meant by an interrupt. … … … … [2] (ii) Explain the actions of the processor when an interrupt is detected. … … … … … … … … … [4]

10 9608/13/M/J/15 © UCLES 2015 6 (a) Three digital sensors A, B and C are used to monitor a process. The outputs from the sensors are used as the inputs to a logic circuit. A signal, X, is output from the logic circuit: logic circuit A B output X C Output, X, has a value of 1 if either of the following two conditions occur: • sensor A outputs the value 1 OR sensor B outputs the value 0 • sensor B outputs the value 1 AND sensor C outputs the value 0 Draw a logic circuit to represent these conditions. A B C X [5]

11 9608/13/M/J/15 © UCLES 2015 [Turn over (b) Complete the truth table for the logic circuit described in part (a). A B C Working Space X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 [4]

12 9608/13/M/J/15 © UCLES 2015 (c) Write a logic statement that describes the following logic circuit. A B C X … … … … [3]

13 9608/13/M/J/15 © UCLES 2015 [Turn over Question 7 begins on page 14.

14 9608/13/M/J/15 © UCLES 2015 7 The table shows assembly language instructions for a processor which has one general purpose register, the Accumulator (ACC). Instruction Explanation Op code Operand LDD <address> Direct addressing. Load contents of given address to ACC STO <address> Store the contents of ACC at the given address LDI <address> Indirect addressing. The address to be used is at the given address. Load the contents of this second address to ACC LDX <address> Indexed addressing. Form the address from <address> + the contents of the index register. Copy the contents of this calculated address to ACC INC <register> Add 1 to contents of the register (ACC) JMP <address> Jump to the given address END Return control to operating system The diagram shows the contents of the memory. Main memory 120 0 0 0 0 1 0 0 1 121 0 1 1 1 0 1 0 1 122 1 0 1 1 0 1 1 0 123 1 1 1 0 0 1 0 0 124 0 1 1 1 1 1 1 1 125 0 0 0 0 0 0 0 1 126 0 1 0 0 0 0 0 1 127 0 1 1 0 1 0 0 1 200 1 0 0 0 1 0 0 0

15 9608/13/M/J/15 © UCLES 2015 [Turn over (a) (i) Show the contents of the Accumulator after execution of the instruction: LDD 121 Accumulator: [1] (ii) Show the contents of the Accumulator after execution of the instruction: LDI 124 Accumulator: Explain how you arrived at your answer. … … … … [3] (iii) Show the contents of the Accumulator after execution of the instruction: LDX 120 Index Register: 0 0 0 0 0 1 1 0 Accumulator: Explain how you arrived at your answer. … … … … [3]

16 9608/13/M/J/15 © UCLES 2015 (b) Trace the assembly language program using the trace table. 300 LDD 321 301 INC 302 STO 323 303 LDI 307 304 INC 305 STO 322 306 END 307 320 320 49 321 36 322 0 323 0 Trace table: Accumulator Memory address 320 321 322 323 49 36 0 0 [6] Permission to reproduce items where third-party owned material protected by copyright is included has been sought and cleared where possible. Every reasonable effort has been made by the publisher (UCLES) to trace copyright holders, but if any items requiring clearance have unwittingly been included, the publisher will be pleased to make amends at the earliest possible opportunity. To avoid the issue of disclosure of answer-related information to candidates, all copyright acknowledgements are reproduced online in the Cambridge International Examinations Copyright Acknowledgements Booklet. This is produced for each series of examinations and is freely available to download at www.cie.org.uk after the live examination series. Cambridge International Examinations is part of the Cambridge Assessment Group. Cambridge Assessment is the brand name of University of Cambridge Local Examinations Syndicate (UCLES), which is itself a department of the University of Cambridge.

® IGCSE is the registered trademark of Cambridge International Examinations. CAMBRIDGE INTERNATIONAL EXAMINATIONS Cambridge International Advanced Subsidiary and Advanced Level MARK SCHEME for the May/June 2015 series 9608 COMPUTER SCIENCE 9608/13 Paper 1 (Written Paper), maximum raw mark 75 This mark scheme is published as an aid to teachers and candidates, to indicate the requirements of the examination. It shows the basis on which Examiners were instructed to award marks. It does not indicate the details of the discussions that took place at an Examiners’ meeting before marking began, which would have considered the acceptability of alternative answers. Mark schemes should be read in conjunction with the question paper and the Principal Examiner Report for Teachers. Cambridge will not enter into discussions about these mark schemes. Cambridge is publishing the mark schemes for the May/June 2015 series for most Cambridge IGCSE®, Cambridge International A and AS Level components and some Cambridge O Level components.

Page 2 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 1 (a) (i) 124 0 1 1 1 1 1 0 0 –77 1 0 1 1 0 0 1 1 [2] (ii) 124: 7 C –77: B 3 [2] (b) (i) 0 0 1 1 0 1 0 1 1 0 0 1 [1] (ii) • when denary numbers need to be electronically coded • e.g. to operate displays on a calculator where each digit is represented • decimal fractions can be accurately represented [2] 2 Activity First pass or second pass any symbolic address is replaced by an absolute address 2 any directives are acted upon 1 any symbolic address is added to the symbolic address table 1 data items are converted into their binary equivalent 1 forward references are resolved 2 [5]

Page 3 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 3 (a) maximum of two marks for firewall description + maximum of two marks for authentication description Firewall • sits between the computer or LAN and the Internet/WAN and permits or blocks traffic to/from the network • can be software and/or hardware • software firewall can make precise decisions about what to allow or block as it can detect illegal attempts by specific software to connect to Internet • can help to block hacking or viruses reaching a computer Authentication • process of determining whether somebody/something is who/what they claim to be • frequently done through log on passwords/biometrics • because passwords can be stolen/cracked, digital certification is used • helps to prevent unauthorised access to data [3] (b) one mark for security, one mark for integrity: • integrity deals with validity of data/freedom from errors/data is reasonable • security deals with protection of data • security protects data from illegal access/loss • integrity deals with making sure data is not corrupted after, for example, being transmitted [2] (c) (i) one mark for each way of maintaining data security + one mark for an example/ enhancement • validation (to ensure data is reasonable) • examples include range checks, type checks, length checks, … • verification (checks if data input matches original/if transmitted data matches original) • can use double data entry or visual check/other methods such as parity checks • doesn’t check whether or not data is reasonable [3] (ii) one mark for each way of maintaining data integrity + one mark for an example/ enhancement • parity checking • one of the bits is reserved as parity bit • e.g. 1 0 1 1 0 1 1 0 uses odd parity • number of 1s must be odd • parity is checked at receiver’s end • a change in parity indicates data corruption • check sum • adds up bytes in data being sent and sends check sum with the data • calculation is re-done at receiver’s end • if not the same sum then the data has been corrupted during transmission [3]

Page 4 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 4 (a) [5] requires data to be refreshed periodically in order to retain the data has more complex circuitry does not need to be refreshed as the transistors hold the data as long as the power supply is on requires higher power consumption which is significant when used in battery-powered devices used predominantly in cache memory of processors where speed is important DRAM SRAM

Page 5 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 (b) maximum of two marks for RAM and maximum of two marks for ROM RAM • loses contents when power turned off/volatile memory/temporary memory • stores files/data/operating system currently in use • data can be altered/deleted/read from and written to • memory size is often larger than ROM ROM • doesn’t lose contents when power turned off/non-volatile memory/permanent memory • cannot be changed/altered/deleted/read only • can be used to store BIOS/bootstrap [3] (c) one mark for DVD-RAM, one mark for flash memory. DVD-RAM • data is stored/written using lasers/optical media • DVD-RAM uses phase changing recording, in which varying laser intensities cause targeted areas in the phase change recording layer to alternate between an amorphous and a crystalline state. • uses a rotating disk with concentric tracks • allows read and write operation to occur simultaneously flash memory • most are NAND-based flash memory • there are no moving parts • uses a grid of columns and rows that has two transistors at each intersection • one transistor is called a floating gate • the second transistor is called the control gate • memory cells store voltages which can represent either a 0 or a 1 • essentially the movement of electrons is controlled to read/write • not possible to over-write existing data; it is necessary to first erase the old data then write the new data in the same location [2]

Page 6 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 5 (a) one mark for name of bus + one mark for description address bus • lines used to transfer address of memory or input/output location • unidirectional bus data bus • used to transfer data between the processor and memory/input and output devices • bidirectional bus control bus • used to transmit control signals • e.g. read/write/fetch/ … • dedicated bus since all timing signals are generated according to control signal [6] (b) (i) the program counter is incremented [1] (ii) the data stored at the address held in MAR is copied into the MDR [1] (iii) the contents of the Memory Data Register is copied into the Current Instruction Register [1] (c) • the MAR is loaded with the operand of the instruction // loaded with 35 • the Accumulator is loaded with the contents of the address held in MAR // the Accumulator is loaded with the contents of the address 35 [2] (d) (i) • a signal • from a device/program that it requires attention from the processor [2] (ii) • at a point during the fetch-execute cycle … • check for interrupt • if an interrupt flag is set/ bit set in interrupt register • all contents of registers are saved • PC loaded with address of interrupt service routine [4]

Page 7 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 6 (a) [5] (b) A B C working X 0 0 0 1 } 1 mark 0 0 1 1 0 1 0 1 } 1 mark 0 1 1 0 1 0 0 1 } 1 mark 1 0 1 1 1 1 0 1 } 1 mark 1 1 1 1 [4]

Page 8 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 (c) ((A is NOT 1 AND B is 1) OR (B is NOT 1 OR C is 1)) AND C is NOT 1 < – – – – – 1 mark – – – – – > < – – – – – 1 mark – – – – – > < – – – – –1 mark – – – – – > NOTE: all brackets may not be shown – but check answer still correct Alternatives include: ((NOT A AND B) OR (NOT B OR C)) AND NOT C (A . B + ( B + C)) . C NOTE: expressions may be reversed but still OK (e.g. NOT C AND ((NOT A AND B) OR (NOT B OR C)) NOT C AND ((NOT B OR C) OR (NOT A AND B)) and so on) [3] 7 (a) (i) Accumulator: 0 1 1 1 0 1 0 1 [1] (ii) Accumulator: 0 1 1 0 1 0 0 1 [1] explanation • content of 124 is 0 1 1 1 1 1 1 1 • this is equivalent to 127 • contents of 127 are 0 1 1 0 1 0 0 1 [2] (iii) Accumulator: 0 1 0 0 0 0 0 1 [1] explanation • index register value = 6 • 120 + 6 = 126 • contents of 126 placed in the accumulator [2]

Page 9 Mark Scheme Syllabus Paper Cambridge International AS/A Level – May/June 2015 9608 13 © Cambridge International Examinations 2015 (b) 1 mark for each correct value in the table. Accumulator Memory address 320 321 322 323 49 36 0 0 36 37 37 49 50 50 [6]